1. Field of the Invention
The present invention relates to a fabrication method for miniaturized industrial products. In particular, it relates to a fabrication method preferable for development and standardization of a new manufacturing process for a miniaturized structure.
2. Description of the Related Art
For fabrication of a large-scale semiconductor integrated circuit with a minimum feature size F of 100 to 150 nm or less, advanced mask processing technology and lithography technology are needed. Particularly as the degree of miniaturization increases, there is increased difficulty in generating a flawless mask having many fine line-and-space patterns.
In addition to a mask level problem, with fabrication of micro-patterns for a semiconductor integrated circuit, there is a serious issue of generation of interconnect pattern defects or element pattern defects due to characteristics of substrate materials, fabrication environment, defective mask patterns, or lithography tool operating technology.
With a fabrication method for a microscopic semiconductor integrated circuit, one problem that occurs on semiconductor wafers includes fluctuations in pattern ends, which may cause short-circuit failure or open-circuit failure in the pattern of the semiconductor integrated circuit. Typically, ascribable to the fluctuations in pattern ends, an allowable error margin is required within the fabrication procedure so as to suppress the problem, and the fluctuations in pattern ends account for dimensional allowance. Accordingly, when a new fabrication procedure for a semiconductor integrated circuit is scheduled to be developed and standardized, or when designing a new semiconductor integrated circuit, with principal patterns serving as the target semiconductor integrated circuit disposed in central and principal area of a chip area, a plurality of evaluation test patterns (circuits) called “test element group (TEG) patterns” are merged in a part of the semiconductor wafer such as the periphery of the chip area so as to evaluate the fabrication procedure, electrical characteristics, fabrication conditions, and circuit functions by the TEG patterns.
A method of measuring electrical characteristics between terminals (pads) of a process testing pattern called “a process level TEG (PL-TEG) pattern” and a method of evaluating (estimating) yield and the like from the results has been adopted for evaluation of each process levels such as polysilicon film growth, impurity diffusion, and metal film formation (see Japanese Patent Application Laid-Open No. 2003-133385). PL-TEG pattern is a pattern of a specific mask (hereafter called “a process-level evaluation mask”) for examining process dependency in order to investigate adverse affects such as causing open-circuit failure or short-circuit failure in the actual device patterns of semiconductor integrated circuit when process conditions for the semiconductor integrated circuit fabrication method vary. The process-level evaluation mask is implemented by closely aligned patterns equivalent to fine line patterns arranged in the semiconductor integrated circuit as a target industrial product, and is intended to easily statistically recognize short-circuit failures or open-circuit failures in the patterns of each process level.
Using semiconductor memory as an example of the target industrial product, each of the chip areas arranged on a semiconductor wafer is occupied by a plurality of semiconductor elements, called memory cells, each of which is configured to store data. Since an increasingly larger number of memory cells may be arranged within the same given area size as micro-fabrication technology of fine patterns advances, the most advanced micro-fabrication technology is typically used for the fabrication of the memory cell patterns during development, and state-of-the-art micro-fabrication technology is used for the fabrication of line patterns and space patterns. Due to this situation in the micro-fabrication technology, production of the process-level evaluation mask is generally carried out at the highest quality presently available, and exclusive masks for flawless patterns are required for examining open-circuit characteristics and short-circuit characteristics of patterns on semiconductor wafers.
Accordingly, production of the process-level evaluation mask is very difficult due to processing limits in each process. Meanwhile, because there are strict demands on transfer of the images of the process-level evaluation mask for examining processing fluctuation in the results of transferring the images onto the semiconductor wafer, the conditions for transferring the images of the process-level evaluation masks onto the semiconductor wafer are strict. Therefore, differences in image-transfer behavior between the process-level evaluation masks and masks routinely employed to the main portion of the semiconductor memory (or the target industrial product) in the actual fabrication sequences (hereafter called “working mask for a target industrial product” or simply “working mask”) is an important factor for determination of the processing fluctuation on the semiconductor wafer, “the main portion of the semiconductor memory” excludes peripheral regions of a chip area where TEG patterns are merged on the semiconductor wafer, if the target industrial product is a semiconductor integrated circuit.
Particularly, it is impossible to precisely evaluate processing fluctuation by the exclusive PL-TEG pattern in the earlier technology, the PL-TEG pattern is implemented by a different pattern disposed on the same mask substrate than that of the actual device pattern, taking into consideration loading effects and the like during lithography and dry etching processes of micro-patterns. This problem emanates from difference in the covering rate of the fine patterns between the actual device pattern and corresponding PL-TEG pattern on the mask substrate. Therefore, it required much labor by doubling the job, because an extra job such as separately finding the correlation between the exclusive PL-TEG mask and the working mask becomes necessary, thereby causing an indeterminate factor in the evaluation of the processing fluctuation. In other words, in the earlier technology, the practical meaning of the method of preparing the exclusive PL-TEG mask separate from the working mask is becoming not as important nowadays where the absolute value of dimensions is becoming smaller, and essentially, covering rate and pattern density of the process-level evaluation mask are required to be the same as the covering rate and the pattern density of the working mask.
Furthermore, in the earlier technology, with extremely miniaturized, high accuracy masks, adverse influences of individual differences of the respective working masks increase, and the method using the exclusive PL-TEG mask is reaching its limit, and the production of the exclusive PL-TEG mask itself is becoming difficult.